Search - VHDL CPLD

[Communication] 用cpld实现曼彻斯特编码2

Description: 此曼彻斯特码的解码程序是采用VHDL硬件语言编写的。-this procedure code decoder VHDL hardware is used to prepare the language.
Platform: | Size: 3542 | Author: 游畅 | Hits:

[Other resource] CPLD的跑馬燈

Description: cpld的入门交流：CPLD的跑馬燈一个简易型cpld试验电路用VHDL语言遍的-cpld entry exchange : CPLD 5,250 cpld an easy-to-use test circuit using VHDL times the
Platform: | Size: 64883 | Author: 口是心非 | Hits:

[Other resource] CPLD--VHDL

Description: VHDL的基础知识,一切从基础开始!希望这个对大家有所帮助!-VHDL basic knowledge, everything from the foundation started! We hope that the right help!
Platform: | Size: 31033 | Author: 老纪 | Hits:

Description: 使用PS2接口的键盘的小键盘输入，在12864液晶上显示出来，使用平台为CPLD或FPGA-PS2 keyboard interface to use a small keyboard input, in the 12864 liquid crystal display, use the platform for the CPLD or FPGA
Platform: | Size: 1053696 | Author: luojicheng | Hits:

[VHDL-FPGA-Verilog] CPLD-CRACK-SIEMENS-200PLC

Description: 可用来破解分析西门子200 PLC与模块的通讯协议，基于ALTERA CPLD EPM240的设计. 需要配合分析板配套使用。-Analysis can be used to crack the Siemens 200 PLC and the communication protocol modules, based on the ALTERA CPLD EPM240 design. The need to tie in with the analysis supporting the use of panels.
Platform: | Size: 2048 | Author: wuzhen | Hits:

[VHDL-FPGA-Verilog] CPLD

Description: 摘要：本文主要介绍以CPLD 芯片进行十字路口的交通灯的设计，用CPLD 作为交通灯控制器的主控芯片，采用VHDL 语言编写控制程序，利用CPLD的可重复编程和在动态系统重构的特性，大大地提高了数字系统设计的灵活性和通用性。关键词：CPLD；VHDL；交通灯控制器中图分类号：TP39 Abstract ：This paper introduces the electronic-traffic lamp, which is based on the VHDL and is completed by-Abstract: This paper introduces the CPLD chip to the traffic lights at the crossroads of design, traffic lights with CPLD as the master controller chip, the use of VHDL language control procedures, the use of CPLD re-programming and dynamic system reconfiguration in the features greatly enhance the digital system design flexibility and versatility. Keywords: CPLD VHDL traffic lights controller CLC number: TP39 Abstract: This paper introduces the electronic-traffic lamp, which is based on the VHDL and is completed by
Platform: | Size: 34816 | Author: jimmy | Hits:

[VHDL-FPGA-Verilog] cpld

Description: 基于ATEREAL EPM1270T144C5N CPLD 压力传感器数据采集原码开发软件 Quartus II -ATEREAL EPM1270T144C5N CPLD-based pressure sensor data acquisition source Quartus II development software
Platform: | Size: 308224 | Author: 胡兵 | Hits:

[Other] VHDL100Examples

Description: CPLD中常见模块设计资料,100个精典的例子-CPLD module design information in common, 100 examples of classical
Platform: | Size: 237568 | Author: kevin | Hits:

[Embeded-SCM Develop] plx9054-localbus-cpld-vhdl-src

Description: PLX 公司 PLX9054 pci target controller local bus interface vhdl programe-PLX inc. PLX9054 pci target controller local bus interface vhdl programe
Platform: | Size: 1024 | Author: richardz | Hits:

[VHDL-FPGA-Verilog] cpld

Description: CPLD VHDL 数码管程序流水灯程序时钟程序 -CPLD VHDL program LED lights water clock procedures procedures CPLD VHDL program LED lights process water clock procedures
Platform: | Size: 476160 | Author: 朱工 | Hits:

[Embeded-SCM Develop] CPLD

Description: 风力发电设备用CPLD外围控制程序。包括故障锁存，IO口输出输入，地址线译码等。-Wind power generation equipment control procedures external CPLD. Including the fault latch, IO I O, address decoding and other lines.
Platform: | Size: 73728 | Author: 吕佃顺 | Hits:

[Embeded-SCM Develop] deCPLDVHDLshijong

Description: 基于CPLD的VHDL语言数字钟（含秒表）设计利用一块芯片完成除时钟源、按键、扬声器和显示器（数码管）之外的所有数字电路功能。所有数字逻辑功能都在CPLD器件上用VHDL语言实现。这样设计具有体积小、设计周期短（设计过程中即可实现时序仿真）、调试方便、故障率低、修改升级容易等特点。本设计采用自顶向下、混合输入方式（原理图输入—顶层文件连接和VHDL语言输入—各模块程序设计）实现数字钟的设计、下载和调试。 -CPLD based on the VHDL language digital clock (with stopwatch) design using a chip can be completed in addition to the clock source, buttons, speakers and display (LED) in addition to all functions of digital circuits. All digital logic functions are used in the CPLD device VHDL language. This design has a small and short design cycle (design process to achieve timing simulation), to facilitate debugging, fault rate is low and easy to modify the characteristics of the upgrade. The design uses a top-down, mixed input (input schematic- top-level file access and VHDL language input- the module program design) Design of digital clock, download and debug.
Platform: | Size: 95232 | Author: wuhuisong | Hits:

[VHDL-FPGA-Verilog] 48led

Description: 此软件用的是QuartusII 5.1的环境编写的CPLD内的程序，CPLD用的是EPM7128，实现的功能是对计算机的ISA总线读写操作，计算机通过ISA总线，再通过CPLD，来控制LED的亮和灭-This software is used in the preparation of QuartusII 5.1 environment within the CPLD procedures, CPLD using EPM7128, the function of the realization of the ISA bus on the computer to read and write operation, the computer through the ISA bus, and then through the CPLD, to control the LED' s Liang and poverty
Platform: | Size: 201728 | Author: hujianhua | Hits:

[Com Port] rs232

Description: 这是cpld，EPM240数据通信rs232程序，希望与大家分享-This is cpld, EPM240 data communication rs232 procedure, hoping to share with you
Platform: | Size: 132096 | Author: 蓝风 | Hits:

[VHDL-FPGA-Verilog] counter-CPLD

Description: CPLD学习，用VHDL,应用EPM7032,一个138，373和273的例程-CPLD study, using VHDL, application EPM7032, one of the routines 138,373, and 273
Platform: | Size: 100352 | Author: YAN | Hits:

[VHDL-FPGA-Verilog] UART-CPLD

Description: 使用VHDL在CPLD上设计UART的一个项目-VHDL design UART
Platform: | Size: 6302720 | Author: yuyue | Hits:

[Software Engineering] vhdl-TAXI

Description: 随着EDA技术的发展及大规模可编程逻辑器件CPLD／FPGA的出现，电子系统的设计技术和工具发生了巨大的变化，通过EDA技术对CPLD／FPGA编程开发产品，不仅成本低、周期短、可靠性高，而且可随时在系统中修改其逻辑功能。本文利用VHDL语言设计出租车计费系统，使其实现汽车启动、停止、暂停时计费以及预置等功能，通过设置计数电路进行路费及路程的计数，通过设计数据转换电路将路费及路程的十进制数分离成四位十进制数表示，通过设计快速扫描电路显示车费及路费，突出了其作为硬件描述语言的良好的可读性的优点。通过MAX+PLUSⅡ软件编写、调试和优化源程序，下载到特定芯片（MAX系列的EPM 7128SLC8415）后，即可应用于实际的出租车计费系统中。-ith the development of EDA technologies and large-scale programmable logic device CPLD/FPGA emergence of electronic systems design techniques and tools has undergone tremendous changes, through the EDA technology CPLD/FPGA programming product development, not only low-cost, short lead time, high reliability, but also may at any time in the system to modify its logic function. In this paper, VHDL language design taxi billing system to achieve the car to start, stop, pause, time billing and preset functions, by setting the tolls and the distance counting circuit count, through the design of data conversion circuits and the journey will be toll separated into four decimal decimal number, said a quick scan through the design of the circuit shows fares and tolls, highlighting its position as a hardware description language, the advantages of good readability. Through the MAX+ PLUS Ⅱ software development, debugging and optimizing the source code, download to a specific chip (MAX series of EP
Platform: | Size: 269312 | Author: stella | Hits:

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[Communication] 用cpld实现曼彻斯特编码2

[Other resource] CPLD的跑馬燈

[Other resource] CPLD--VHDL

[Windows Develop] lcd

[VHDL-FPGA-Verilog] CPLD-CRACK-SIEMENS-200PLC

[VHDL-FPGA-Verilog] CPLD

[VHDL-FPGA-Verilog] cpld

[Other] VHDL100Examples

[Embeded-SCM Develop] plx9054-localbus-cpld-vhdl-src

[VHDL-FPGA-Verilog] cpld

[Embeded-SCM Develop] CPLD

[Embeded-SCM Develop] deCPLDVHDLshijong

[VHDL-FPGA-Verilog] 48led

[Com Port] rs232

[VHDL-FPGA-Verilog] counter-CPLD

[VHDL-FPGA-Verilog] UART-CPLD

[Software Engineering] vhdl-TAXI

[VHDL-FPGA-Verilog] CPLD

[VHDL-FPGA-Verilog] VHDL-CPLD

[VHDL-FPGA-Verilog] 基于CPLD的万年历的设计

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